Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs
نویسندگان
چکیده
A new set of benchmark designs is presented together with a reference experiment flow based on state of the art industrial and academic tools. Interfacing the tools became possible by extending the academic design specification format (BLIF) with the capability to represent blocks with unknown logic specification. This extension is required for handling large HDL designs containing memories and blackboxes. All tools and designs are made publicly available in an attempt to standardize on a benchmarking method for future tool evaluations and extensions to placement, routing, and other CAD algorithms.
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